C8051F018
25 MIPS, 16 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 µC Core
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±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
16 programmable hysteresis values
Configurable to generate interrupts or reset
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
1280 bytes data RAM
16 kB Flash; in system programmamble in 512-byte sectors (512 bytes
are reserved)
32 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules
4 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
64-pin TQFP (standard lead and lead-free packages)
Lead-free package: C8051F018-GQ
Standard package: C8051F018
Memory
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
Digital Peripherals
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
Typical operating current: 12.5 mA at 25 MHz
Multiple power saving sleep and shutdown modes
Clock Sources
Supply Voltage: 2.8 to 3.6 V
Temperature Range: –40 to +85 °C
Package
Ordering Part Numbers
VDD
VDD
VDD
DGND
DGND
DGND
A
V+
A
V+
A
GND
A
GND
TCK
TMS
TDI
TDO
RST
Digital Power
UART
SMBus
SPI Bus
Analog Power
5-Chnl
PCA
Boundary Scan
Debug HW
Reset
JTAG
Logic
VDD
Monitor
XTAL1
XTAL2
WDT
8
0
5
1
C
o
r
e
16 kB
FLASH
256 Byte
RAM
1024 Byte
XRAM
Timers
0,1,2
Timer 3
Port 0
Latch
Port 1
Latch
Port 2
Latch
C
R
O
S
S
B
A
R
S
W
I
T
C
H
P
0
D
r
v
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
External
Oscillator
Circuit
Internal
Oscillator
System Clock
SFR Bus
Port 3
Latch
VREF
VREF
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
A
M
U
X
TEMP
SENSOR
ADC
100 ksps
(10-Bit)
NC
NC
CP0
CP1
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
5.5.2005
SILABS [ SILICON LABORATORIES ]
