C8051F226
25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
8-Bit ADC
High-Speed 8051 µC Core
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±1/2 LSB INL; no missing codes
Programmable throughput up to 100 ksps
32 external inputs (each port I/O can be configured as an ADC input on-
the-fly)
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
V
REF
from external pin or V
DD
Programmable hysteresis
Configurable to generate interrupts or reset
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler; up to 21 interrupt sources
1280 bytes data RAM
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
32 port I/O; all are 5 V tolerant
Hardware SPI™ and UART serial ports available concurrently
3 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 9 mA at 25 MHz
Typical stop mode current: <0.1 uA
Memory
Two comparators
Digital Peripherals
V
DD
Monitor and Brown-out Detector
On-Chip JTAG Debug
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Clock Sources
Supply Voltage: 2.7 to 3.6 V
48-Pin TQFP
-
Temperature Range: –40 to +85 °C
VDD
VDD
GND
GND
NC
NC
NC
Analog/Digital
Power
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
P
0
M
U
X
P
0
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
TCK
TMS
TDI
TDO
RST
JTAG
Logic
Debug HW
Reset
8
0
5
1
C
o
r
e
8 kB FLASH
256 byte
RAM
1024 byte
XRAM
Port 1
Latch
CP0
CP0+
CP0
P
1
M
U
X
P
1
D
r
v
CP0-
CP1+
CP1
CP1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
MONEN
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
CP1-
SYSCLK
WDT
XTAL1
XTAL2
SFR Bus
Port 2
Latch
SPI
P
2
M
U
X
P
2
D
r
v
P
3
System Clock
P2.0/NSS
P2.1/MISO
P2.2/MOSI
P2.3/SCK
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 3
Latch
D
r
v
8-bit
100 ksps
ADC
VDD
PGA
A
M
U
X
AIN0-AIN31
VREF
General Purpose
Copyright © 2004 by Silicon Laboratories
6.15.2004
SILABS [ SILICON LABORATORIES ]
