C8051F310/1/2/3/4/5/6/7
18.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
PCA Interrupt
PCA0CPMn
P
ECCMT
P
E
W
C A A AO
W
C
M
OPP TG
M
C
1
MPN n n
n
F
6
n n n
n
n
x 0
x 0 0 x
PCA0CN
CC
FR
CCCCC
CCCCC
FF FFF
4 3 2 1 0
(to CCFn)
PCA0CPLn
PCA0CPHn
0
Port I/O
Crossbar
CEXn
1
0
1
PCA
Timebase
Capture
PCA0L
PCA0H
Figure 18.4. PCA Capture Mode Diagram
Note:
The CEXn input signal must remain high or low for at least 2 system clock cycles in order to be valid.
206
Rev. 1.7
SILABS [ SILICON LABORATORIES ]
