C8051F310/1/2/3/4/5/6/7
18.2.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod-
ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted
low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match inter-
rupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn
register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help
synchronize the capture/compare register writes. The duty cycle for 16-Bit PWM Mode is given by
Equation 18.3.
Important Note About Capture/Compare Registers:
When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Equation 18.3. 16-Bit PWM Duty Cycle
(
65536 –
PCA0CPn
)
-
DutyCycle
= ----------------------------------------------------
65536
Using Equation 18.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Write to
PCA0CPLn
Reset
Write to
PCA0CPHn
0
ENB
ENB
1
PCA0CPMn
P
ECCMT
P
E
W
C A A AO
W
C
M
OPP TG
M
C
1
MPN n n
n
F
6
n n n
n
n
1
0 0 x 0
x
Enable
PCA0CPHn
PCA0CPLn
16-bit Comparator
match
S
SET
Q
CEXn
Crossbar
Port I/O
R
PCA Timebase
CLR
Q
PCA0H
PCA0L
Overflow
Figure 18.9. PCA 16-Bit PWM Mode
Rev. 1.7
211
SILABS [ SILICON LABORATORIES ]
