C8051F310/1/2/3/4/5/6/7
19.3. PCA Counter
On “REV A” devices, if the main PCA counter (PCA0H : PCA0L) overflows during the execution phase of a
read-modify-write instruction (bit-wise SETB or CLR, ANL, ORL, XRL) that targets the PCA0CN register,
the CF (Counter Overflow) bit will not be set. An example software work-around is as follows:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Disable global interrupts (EA = 0).
Read PCA0L. This will latch the value of PCA0H.
Read PCA0H, saving the value.
Execute the bit-wise operation on CCFn (for example, CLR CCF0, or CCF0 = 0;).
Read PCA0L.
Read PCA0H, saving the value.
If the value of PCA0H read in Step 3 is 0xFF and the value for PCA0H read in Step 6 is
0x00, then manually set the CF bit in software (for example, SETB CF, or CF = 1;).
Step 8. Re-enable interrupts (EA = 1).
This behavior is not present on “REV B” and later devices. Software written for “REV A” devices will run on
“REV B” and later devices without modification.
222
Rev. 1.7
SILABS [ SILICON LABORATORIES ]
