C8051F310/1/2/3/4/5/6/7
1.2.
On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 8 or 16 kB of Flash. This memory may be reprogrammed in-system in 512
byte sectors, and requires no special off-chip programming voltage. See Figure 1.11 for the MCU system
memory map.
PROGRAM/DATA MEMORY
(Flash)
C8051F310/1/6/7
0x3E00
0x3DFF
RESERVED
0x80
0x7F
0xFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Special Function
Register's
(Direct Addressing Only)
16 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
0x0000
0xFFFF
C8051F312/3/4/5
0x2000
0x1FFF
RESERVED
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1 kB boundaries
8 kB Flash
(In-System
Programmable in 512
Byte Sectors)
0x0400
0x03FF
0x0000
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
Figure 1.11. On-Board Memory Map
Rev. 1.7
29
SILABS [ SILICON LABORATORIES ]
