C8051F310/1/2/3/4/5/6/7
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F31x
Name
V
DD
GND
RST/
5
C2CK
P3.0/
6
C2D
P0.0/
2
VREF
P0.1
P0.2/
32
XTAL1
P0.3/
31
XTAL2
P0.4
P0.5
P0.6/
28
CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
27
26
25
24
23
22
23
22
21
20
19
18
19
18
17
16
15
14
D I/O
24
20
ADC0 External Convert Start Input. (‘F310/1/2/3 only)
Port 0.7. See
for a complete description.
D I/O or
Port 1.0. See
for a complete description.
A In
D I/O or
Port 1.1. See
for a complete description.
A In
D I/O or
Port 1.2. See
for a complete description.
A In
D I/O or
Port 1.3. See
for a complete description.
A In
D I/O or
Port 1.4. See
for a complete description.
A In
30
29
26
25
22
21
27
23
28
24
A In
D I/O
1
1
1
2
2
A In
D I/O
D I/O
External VREF input. (‘F310/1/2/3 only)
Port 0.1. See
for a complete description.
Port 0.2. See
for a complete description.
External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
Port 0.3. See
for a complete description.
6
6
D I/O
D I/O
Bi-directional data signal for the C2 Debug Interface.
Port 0.0. See
for a complete description.
5
5
D I/O
D I/O
Pin Numbers
‘F310/2/4 ‘F311/3/5 ‘F316/7
4
3
4
3
4
3
D I/O
Type
Description
Power Supply Voltage.
Ground.
Device Reset. Open-drain output of internal POR. An
external source can initiate a system reset by driving
this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
Port 3.0. See
for a complete description.
External Clock Output. For an external crystal or reso-
A Out or nator, this pin is the excitation driver. This pin is the
D In external clock input for CMOS, capacitor, or RC oscil-
lator configurations.
D I/O
D I/O
Port 0.4. See
for a complete description.
Port 0.5. See
for a complete description.
Port 0.6. See
for a complete description.
Rev. 1.7
39
SILABS [ SILICON LABORATORIES ]
