C8051F336/7/8/9
19.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F336/7/8/9 devices include a programmable internal high-frequency oscillator that defaults as
the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL regis-
ter as defined by SFR Definition 19.2.
On C8051F336/7/8/9 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8,
as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
19.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
•
•
•
•
Port 0 Match Event.
Port 1 Match Event.
Comparator 0 enabled and output is logic 0.
Timer3 Overflow Event.
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
SFR Definition 19.2. OSCICL: Internal H-F Oscillator Calibration
Bit
7
6
5
4
3
OSCICL[6:0]
R/W
2
1
0
Name
Type
Reset
R
0
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xB3;
Bit
Name
Function
7
UNUSED Unused. Read = 0; Write = Don’t Care
6:0 OSCICL[6:0] Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the H-F
oscillator operates at its fastest setting. When set to 1111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
118
Rev. 0.2
SILICON [ SILICON ]
