C8051F336/7/8/9
20. Port Input/Output
Digital and analog resources are available through 17 (C8051F336/7) or 21 (C8051F338/9) I/O pins. Port
pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 20.3. Port pin P2.4 on the C8051F338/9
and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal
(C2D). The designer has complete control over which functions are assigned, limited only by the number of
physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 6.3 on page 36.
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Rev. 0.2
SILABS [ SILICON LABORATORIES ]
