C8051F336/7/8/9
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
Table 21.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0)
Values to
Write
Values Read
Current SMbus State
Typical Response Options
A master START was gener- Load slave address + R/W into
1110
1100
0
0
0
0
X
0
0
X
1100
ated.
SMB0DAT.
A master data or address byte Set STA to restart transfer.
1
0
0
1
X
X
1110
-
0 was transmitted; NACK
received.
Abort transfer.
Load next data byte into
SMB0DAT.
0
0
1
1
0
1
1
0
X
X
X
X
1100
End transfer with STOP.
-
-
A master data or address byte End transfer with STOP and start
0
0
1 was transmitted; ACK
received.
another transfer.
Send repeated START.
1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
0
0
X
1000
Acknowledge received byte;
Read SMB0DAT.
0
0
0
1
1
0
1000
-
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
1
1
0
1110
Send ACK followed by repeated
START.
A master data byte was
0 X
1
1
0
0
1
0
1110
1110
1000
1
received; ACK requested.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
0
1
0
1100
1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
162
Rev. 0.2
SILICON [ SILICON ]
