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18.2. Power-Fail Reset / V Monitor
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When a power-down transition or power irregularity causes V
to drop below V , the power supply
RST
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monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 18.2). When V returns
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to a level above V
, the CIP-51 will be released from the reset state. Note that even though internal data
RST
memory contents are not altered by the power-fail reset, it is impossible to determine if V dropped below
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the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
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monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V monitor is disabled by code and a software reset is performed, the
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V
monitor will still be disabled after the reset.
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Important Note: If the V monitor is being turned on from a disabled state, it should be enabled before it
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is selected as a reset source. Selecting the V monitor as a reset source before it is enabled and stabi-
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lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V monitor and configuring it as a reset source from a disabled
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state is shown below:
Step 1. Enable the V monitor (VDMEN bit in VDM0CN = ‘1’).
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Step 2. If necessary, wait for the V monitor to stabilize (see Table 6.4 for the V Monitor turn-
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on time).
Step 3. Select the V monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
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See Figure 18.2 for V
monitor timing; note that the power-on-reset delay is not incurred after a V
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monitor reset. See Table 6.4 for complete electrical characteristics of the V monitor.
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112
Rev. 0.2
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