C8051F340/1/2/3/4/5/6/7
14.4. 4x Clock Multiplier
The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed
USB communication (see
). A divided version of
the Multiplier output can also be used as the system clock. See
for details on system clock
and USB clock source selection.
The 4x Clock Multiplier is configured via the CLKMUL register. The procedure for configuring and enabling
the 4x Clock Multiplier is as follows:
1.
2.
3.
4.
5.
6.
Reset the Multiplier by writing 0x00 to register CLKMUL.
Select the Multiplier input source via the MULSEL bits.
Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80).
Delay for >5 µs.
Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0).
Poll for MULRDY => ‘1’.
Important Note: When using an external oscillator as the input to the 4x Clock Multiplier, the exter-
nal source must be enabled and stable before the Multiplier is initialized. See
for
details on selecting an external oscillator source.
SFR Definition 14.5. CLKMUL: Clock Multiplier Control
R/W
R/W
Bit6
R
Bit5
R/W
R/W
R/W
R/W
Bit1
R/W
Bit0
Reset Value
MULEN
Bit7
MULINIT MULRDY
-
Bit4
-
Bit3
-
Bit2
MULSEL
00000000
SFR Address
0xB9
MULEN: Clock Multiplier Enable
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
Bit6:
MULINIT: Clock Multiplier Initialize
This bit should be a ‘0’ when the Clock Multiplier is enabled. Once enabled, writing a ‘1’ to
this bit will initialize the Clock Multiplier. The MULRDY bit reads ‘1’ when the Clock Multiplier
is stabilized.
Bit5:
MULRDY: Clock Multiplier Ready
This read-only bit indicates the status of the Clock Multiplier.
0: Clock Multiplier not ready.
1: Clock Multiplier ready (locked).
Bits4–2: Unused. Read = 000b; Write = don’t care.
Bits1–0: MULSEL: Clock Multiplier Input Select
These bits select the clock supplied to the Clock Multiplier.
Bit7:
MULSEL
00
01
10
11
Selected Clock
Internal Oscillator
External Oscillator
External Oscillator / 2
RESERVED
146
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
