C8051F340/1/2/3/4/5/6/7
16.1. Endpoint Addressing
A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a
bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint
pipes:
Table 16.1. Endpoint Addressing Scheme
Endpoint
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Associated Pipes
Endpoint0 IN
Endpoint0 OUT
Endpoint1 IN
Endpoint1 OUT
Endpoint2 IN
Endpoint2 OUT
Endpoint3 IN
Endpoint3 OUT
USB Protocol Address
0x00
0x00
0x81
0x01
0x82
0x02
0x83
0x03
16.2. USB Transceiver
The USB Transceiver is configured via the USB0XCN register shown in SFR Definition 16.1. This configu-
ration includes Transceiver enable/disable, pull-up resistor enable/disable, and device speed selection
(Full or Low Speed). When bit SPEED = ‘1’, USB0 operates as a Full Speed USB function, and the on-chip
pull-up resistor (if enabled) appears on the D+ pin. When bit SPEED = ‘0’, USB0 operates as a Low Speed
USB function, and the on-chip pull-up resistor (if enabled) appears on the D- pin. Bits4-0 of register
USB0XCN can be used for Transceiver testing as described in SFR Definition 16.1. The pull-up resistor is
enabled only when VBUS is present (see
for details on
VBUS detection).
Important Note: The USB clock should be active before the Transceiver is enabled.
168
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
