C8051F340/1/2/3/4/5/6/7
18. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in
). Received data buffering allows
UART0 to start reception of a second incoming data byte before software has finished reading the previous
data byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers.
Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF0
TB80
SET
D
CLR
Q
SBUF0
(TX Shift)
TX0
Crossbar
Zero Detector
Stop Bit
Start
Tx Clock
Shift
Data
Tx Control
Tx IRQ
Send
SCON
S0MODE
MCE0
REN0
TB80
RB80
TI0
RI0
UART0 Baud
Rate Generator
TI0
RI0
Serial
Port
Interrupt
Port I/O
Rx IRQ
Rx Clock
Rx Control
Start
Shift
0x1FF
RB80
Load
SBUF0
Input Shift Register
(9 bits)
Load SBUF0
SBUF0
(RX Latch)
Read
SBUF0
SFR Bus
RX0
Crossbar
Figure 18.1. UART0 Block Diagram
Rev. 1.0
215
SILABS [ SILICON LABORATORIES ]
