C8051F340/1/2/3/4/5/6/7
SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Reset Value
00000000
Bit0
SFR Address:
0x99
Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis-
sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con-
tents of the receive latch.
Rev. 1.0
221
SILICON [ SILICON ]
