C8051F340/1/2/3/4/5/6/7
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compil-
ers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard
8052, including four 16-bit counter/timers, two full-duplex UARTs with extended baud rate configuration, an
enhanced SPI port, up to 4352 Bytes of on-chip RAM, 128 byte Special Function Register (SFR) address
space, and up to 40 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions listed by
the required execution time.
Clocks to Execute
Number of Instructions
1
26
2
50
2/3
5
3
14
3/4
7
4
3
4/5
1
5
2
8
1
1.1.3. Additional Features
The C8051F340/1/2/3/4/5/6/7 SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the stan-
dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip V
monitor (forces reset
DD
when power supply voltage drops below V
as given in Table 11.1 on page 111), the USB controller
RST
(USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detec-
tion from Comparator0, a forced software reset, an external reset pin, and an errant Flash read/write pro-
tection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software. The WDT may be permanently enabled in software after a power-on reset during
MCU initialization.
The high-speed internal oscillator is factory calibrated to 12 MHz ±1.5%. A clock recovery mechanism
allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed
mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscil-
lators may also be used with the 4x Clock Multiplier. An internal low-frequency oscillator is also included to
aid applications where power savings are critical. Also included is an external oscillator drive circuit, which
allows an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system
clock. The system clock may be configured to use ether of the internal oscillators, an external oscillator, or
the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly
between oscillator sources. The low-frequency internal oscillator or an external oscillator can be useful in
low power applications, allowing the MCU to run from a slow (power saving) external clock source, while
periodically switching to a higher-speed clock source when fast throughput is necessary.
Rev. 1.0
23
SILICON [ SILICON ]
