C8051F340/1/2/3/4/5/6/7
SFR Definition 19.3. SBUF1: UART1 Data Buffer
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Reset Value
00000000
Bit0
SFR Address:
0xD3
Bits7–0: SBUF1[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB)
This SFR is used to both send data from the UART and to read received data from the
UART1 receive FIFO.
Write: Writing a byte to SBUF1 initiates the transmission. When data is written to SBUF1, it
first goes to the Transmit Holding Register, where it is held for serial transmission. When the
transmit shift register is available, data is transferred into the shift register, and SBUF1 may
be written again.
Read: Reading SBUF1 retrieves data from the receive FIFO. When read, the oldest byte in
the receive FIFO is returned, and removed from the FIFO. Up to three bytes may be held in
the FIFO. If there are additional bytes available in the FIFO, the RI1 bit will remain at logic
‘1’, even after being cleared by software.
SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved SB1RUN Reserved Reserved Reserved Reserved SB1PS1 SB1PS0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xAC
Bit7:
Bit6:
RESERVED: Read = 0b; Must write 0b.
SB1RUN: Baud Rate Generator Enable.
0: Baud Rate Generator is disabled. UART1 will not function.
1: Baud Rate Generator is enabled.
Bits5–2: RESERVED: Read = 0000b; Must write 0000b.
Bits1–0: SB1PS[1:0]: Baud Rate Prescaler Select.
00: Prescaler = 12
01: Prescaler = 4
10: Prescaler = 48
11: Prescaler = 1
230
Rev. 1.0
SILICON [ SILICON ]
