C8051F340/1/2/3/4/5/6/7
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
TMR2CN
T T T T T T T T
F F F 2 2 R 2 2
2 2 2 C S 2 C X
H L L E P S C
CKCON
E
N
L
I
S L
K
T T T T T T S S
3 3 2 2 1 0 C C
MMM MMM A A
T
Enable
Capture
Interrupt
TMR2RLH
H L H L
1 0
SYSCLK / 12
0
1
0
External Clock / 8
TCLK
TMR2H
To SMBus
TR2
1
Capture
TMR2RLL
SYSCLK
1
0
To ADC,
SMBus
TCLK
TMR2L
USB Start-of-Frame (SOF)
0
Low-Frequency Oscillator
Falling Edge
1
T2CSS
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’)
258
Rev. 1.0
SILICON [ SILICON ]
