C8051F340/1/2/3/4/5/6/7
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
TMR3CN
T T T T T T T T
F F F 3 3 R 3 3
3 3 3 C S 3 C X
H L L E P S C
CKCON
E
N
L
I
S L
K
T T T T T T S S
3 3 2 2 1 0 C C
M MM MMM A A
T
Enable
Capture
Interrupt
TMR3RLH
H L H L
1 0
SYSCLK / 12
0
1
0
1
External Clock / 8
TCLK
TMR3H
To ADC
TR3
Capture
TMR3RLL
SYSCLK
1
0
TCLK
TMR3L
USB Start-of-Frame (SOF)
0
Low-Frequency Oscillator
Falling Edge
1
T3CSS
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)
264
Rev. 1.0
SILICON [ SILICON ]
