C8051F410/1/2/3
ning of each series of consecutive reads. Software must check if the smaRTClock Interface is busy prior to
reading RTC0DAT. Autoread is enabled by setting AUTORD (RTC0ADR.6) to logic 1.
20.1.4. RTC0ADR Autoincrement Feature
For ease of reading and writing the 48-bit CAPTURE and ALARM values, RTC0ADR automatically incre-
ments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of setting
an alarm or reading the current smaRTClock timer value.
Table 20.1. smaRTClock Internal Registers
smaRTClock smaRTClock
Register Name
Description
Address
Register
0x00 - 0x05
CAPTUREn smaRTClock Capture
Registers
Six Registers used for setting the 47-bit
smaRTClock timer or reading its current
value. The LSB of CAPTURE0 is not used.
0x06
0x07
RTC0CN
smaRTClock Control
Register
Controls the operation of the smaRTClock
State Machine.
RTC0XCN smaRTClock Oscillator
Control Register
Controls the operation of the smaRTClock
Oscillator.
0x08–0x0D
ALARMn
smaRTClock Alarm
Registers
Six registers used to set or read the 47-bit
smaRTClock alarm value. The LSB of
ALARM0 is not used.
0x0E
0x0F
RAMADDR smaRTClock Backup RAM Used as an index to the 64 byte smaRTClock
Indirect Address Register backup RAM.
RAMDATA smaRTClock Backup RAM Used to read or write the byte pointed to by
Indirect Data Register
RAMADDR.
Rev. 1.0
179
SILICON [ SILICON ]
