C8051F410/1/2/3
VIO
(to rest of chip)
VREGIN
VREG
P0.0/IDAC0
P
Port 0
Latch
P0.1/IDAC1
P0.2
0
VDD
(to smaRTClocl Block)
P0.3
VRTC-BACKUP
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
Port 1
Latch
D
r
v
Battery Switch-Over Circuit
(VDD >= VRTC-BACKUP)
GND
UART
C
R
O
S
S
B
A
R
C2D
P1.0/XTAL1
P1.1/XTAL2
P1.2/VREF
P1.3
P1.4
P1.5
x16
16 kB
FLASH
P
1
Debug HW
8
0
5
1
Timer
0,1,2,3
Reset
256 B
SRAM
D
r
v
/RST/C2CK
PCA x6 /
WDT
P1.6
P1.7
Brown-
Out
POR
2 kB
XRAM
SMBus
SPI
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7/C2D
P
2
C
o
r
SFR Bus
XTAL1
XTAL2
External
Oscillator
Circuit
D
r
v
Port 2
Latch
Clock
Mult.
CRC
Engine
IDAC0
IDAC1
e
12-bit
IDAC0
24.5 MHz
2% Oscillator
CP0
+
-
12-bit
IDAC1
CP1
+
-
32 KHz
Oscillator
XTAL3
XTAL4
64B RAM
VDD
VREF
Temp
A
M
U
X
smaRTClock
State
Machine
12-bit
200 ksps
ADC
smaRTClock Alarm
AIN0-AIN23
smaRTClock Block
Figure 1.3. C8051F412 Block Diagram
Rev. 1.0
23
SILICON [ SILICON ]
