C8051F410/1/2/3
1.5.
12-Bit Analog to Digital Converter
The C8051F41x devices include an on-chip 12-bit SAR ADC with a 27-channel single-ended input multi-
plexer and a maximum throughput of 200 ksps. The ADC system includes a configurable analog multi-
plexer that selects the positive ADC input, which is measured with respect to GND. Ports 0–2 are available
as ADC inputs; additionally, the on-chip Temperature Sensor output and the core supply voltage (V
DD
) are
available as ADC inputs. User firmware may shut down the ADC or use it in
Burst Mode
to save power.
Conversions can be started in four ways: a software command, an overflow of Timer 2 or 3, or an external
convert start signal. This flexibility allows the start of conversion to be triggered by software events, a peri-
odic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status bit
and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been accumulated by a hardware
accumulator. The resulting data word is latched into the ADC data SFRs upon completion of a conversion.
When the system clock is slow, Burst Mode allows ADC0 to automatically wake from a low power shut-
down state, acquire and accumulate samples, then re-enter the low power shutdown state without CPU
intervention.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
Configuration, Control, and Data Registers
P0.0
Start
Conversion
AD0BUSY (W)
Timer 3 Overflow
CNVSTR Rising Edge
Timer 2 Overflow
P0.7
P1.0
Burst Mode
Logic
P1.7
P2.0
P2.3-2.6
available on
C8051F410/2
19-to-1
AMUX
12-Bit
SAR
P2.7
ADC
End of
Conversion
Interrupt
16
ADC Data
Registers
Accumulator
Temp
Sensor
VDD
GND
Window Compare
Logic
Window
Compare
Interrupt
Figure 1.7. 12-Bit ADC Block Diagram
1.6.
Two 12-bit Current-Mode DACs
The C8051F41x devices include two 12-bit current-mode Digital-to-Analog Converters (IDACs). The maxi-
mum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA,
1 mA, and 2 mA. A flexible output update mechanism allows for seamless full-scale changes, and supports
jitter-free updates for waveform generation. The IDAC outputs can be merged onto a single port I/O pin for
increased full-scale current output or increased resolution. IDAC updates can be performed on-demand,
scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram
of the IDAC circuitry.
Rev. 1.0
29
SILABS [ SILICON LABORATORIES ]
