C8051F410/1/2/3
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F41x
Name
V
DD
V
IO
GND
V
RTC-BACKUP
V
REGIN
RST/
Pin Numbers
‘F410/2
7
1
6
3
8
‘F411/3
6
28
5
2
7
Type
Description
Core Supply Voltage.
I/O Supply Voltage.
Ground.
smaRTClock Backup Supply Voltage.
On-Chip Voltage Regulator Input.
D I/O
2
1
D I/O
D I/O
Device Reset. Open-drain output of internal POR or V
DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1 k
Ω
pullup to V
IO
is
recommended. See Reset Sources Section for a complete
description.
Clock signal for the C2 Debug Interface.
Port 2.7. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
smaRTClock Oscillator Crystal Input.
complete description.
smaRTClock Oscillator Crystal Input.
complete description.
C2CK
P2.7/
32
C2D
27
D I/O
XTAL3
5
4
A In
XTAL4
P0.0/
4
3
A Out
17
IDAC0
P0.1/
18
IDAC1
P0.2
P0.3
19
20
16
D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
A Out
IDAC0 Output. See IDAC Section for complete description.
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
17
A Out
18
19
IDAC1 Output. See IDAC Section for complete description.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
Rev. 1.0
41
SILABS [ SILICON LABORATORIES ]
