C8051F410/1/2/3
5.
12-Bit ADC (ADC0)
The ADC0 subsystem for the C8051F41x consists of an analog multiplexer (AMUX0) with 27 total input
selections, and a 200 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold,
programmable window detector, and hardware accumulator. The ADC0 subsystem has a special
Burst
Mode
which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low
power shutdown mode without CPU intervention. The AMUX0, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 inputs are single-ended and may be configured to measure P0.0-P2.7, the Temperature Sensor out-
put, V
DD
, or GND with respect to GND. ADC0 is enabled when the AD0EN bit in the ADC0 Control register
(ADC0CN) is set to logic 1, or when performing conversions in Burst Mode. ADC0 is in low power shut-
down when AD0EN is logic 0 and no Burst Mode conversions are taking place.
ADC0MX
AD0PWR3
AD0PWR2
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
ADC0TK
AD0PWR1
AD0PWR0
AD0TM1
AD0TM0
AD0TK1
AD0TK0
AD0EN
ADC0CN
BURSTEN
AD0INT
AD0BUSY
AD0WINT
AD0LJST
AD0CM1
AD0CM0
00
01
10
11
P0.0
Start
Conversion
SYSCLK
Burst Mode
Logic
FCLK
VDD
Start
Conversion
AD0BUSY (W)
Timer 3 Overflow
CNVSTR Input
Timer 2 Overflow
AD0POST
P2.7
VDD
Temp Sensor
AD0TM1:0
AD0PRE
FCLK
REF
P2.3-P2.6 available on
‘F410/2
ADC0H
P1.7
P2.0
12-Bit
SAR
ADC0L
P0.7
P1.0
Burst Mode
Oscillator
25 MHz Max
27-to-1
AMUX
ADC
Accumulator
AD0WINT
Window
Compare
Logic
AD0SC0
AD0RPT1
AD0RPT0
AD0SC4
AD0SC3
AD0SC2
AD0SC1
GND
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 5.1. ADC0 Functional Block Diagram
5.1.
Analog Multiplexer
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0-P2.7,
the on-chip temperature sensor, the core power supply (V
DD
), or ground (GND).
ADC0 is single-ended
and all signals measured are with respect to GND.
The ADC0 input channels are selected using the
ADC0MX register as described in SFR Definition 5.1.
Important Note About ADC0 Input Configuration:
Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2) and write a ‘1’ in the corresponding
Port Latch register Pn (for n = 0,1,2). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding
bit in register PnSKIP (for n = 0,1,2). See
for more Port I/O
configuration details.
Rev. 1.0
51
SILABS [ SILICON LABORATORIES ]
