C8051F410/1/2/3
SFR Definition 6.1. IDA0CN: IDA0 Control
R/W
IDA0EN
Bit7
R/W
Bit6
R/W
IDA0CM
Bit5
R/W
Bit4
R/W
-
R
IDA0RJST
Bit2
R/W
R/W
Reset Value
IDA0OMD
Bit1
01110011
Bit3
Bit0
SFR Address:
0xB9
Bit 7:
IDA0EN: IDA0 Enable Bit.
0: IDA0 Disabled.
1: IDA0 Enabled.
Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select Bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0H.
Reserved. Read = 0b, Write = 0b.
Bit 3:
Bit 2:
IDA0RJST: IDA0 Right Justify Select Bit.
0: IDA0 data in IDA0H:IDA0L is left justified.
1: IDA0 data in IDA0H:IDA0L is right justified.
Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select Bits.
00: 0.25 mA full-scale output current.
01: 0.5 mA full-scale output current.
10: 1.0 mA full-scale output current.
11: 2.0 mA full-scale output current.
SFR Definition 6.2. IDA0H: IDA0 Data High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Reset Value
00000000
Bit0
SFR Address:
0x97
Bits 7–0: IDA0 Data Word High-Order Bits.
For IDA0RJST = 0:
Bits 7-0 hold the most significant 8-bits of the 12-bit IDA0 Data Word.
For IDA0RJST = 1:
Bits 3-0 hold the most significant 4-bits of the 12-bit IDA0 Data Word. Bits 7-4 are 0000b.
Rev. 1.0
71
SILICON [ SILICON ]
