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C8051F531A-IM 参数 Datasheet PDF下载

C8051F531A-IM图片预览
型号: C8051F531A-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 25 MIPS , 8 kB的闪存, 12位ADC , 20引脚汽车MCU [25 MIPS, 8 kB Flash, 12-Bit ADC, 20-Pin Automotive MCU]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 1 页 / 85 K
品牌: SILABS [ SILICON LABORATORIES ]
   
C8051F531A
25 MIPS, 8 kB Flash, 12-Bit ADC, 20-Pin Automotive MCU
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 16 external inputs
High-Speed 8051 µC Core
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±1 LSB INL; guaranteed monotonic
Programmable throughput up to 200 ksps
Data-dependent windowed interrupt generator
Programmable gain maximizes input signal span
Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
Up to 25 MIPS throughput
8 kB Flash; in-system programmable; flexible security features
256 bytes data RAM
Up to 16 digital I/O; all are 5 V push-pull
SPI™ and UART serial ports available concurrently
Programmable 16-bit counter array with three capture/compare modules
Three general-purpose 16-bit counter/timers
Internal programmable 0.5% oscillator: Up to 25 MHz
External oscillator: Crystal, RC, C, or CMOS Clock
C8051F531A-IT, 20-Pin TSSOP (RoHS-compliant), 6 x 6 mm
2
C8051F531A-IM, 20-Pin QFN (RoHS-compliant), 4 x 4 mm
2
Memory
Built-in Temperature Sensor (±3 °C)
Programmable Comparator
Precision Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip Debug
Digital Peripherals
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watch-points
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Clock Sources
Ordering Part Numbers
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
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Multiple power saving sleep and shutdown modes
Development Kit: C8051F530ADK
Power On
Reset
Reset
CIP-51 8051 Controller
Core (25 MHz)
8 kB Flash Program
Memory
256 Byte SRAM
Port I/O Configuration
VREGIN
Digital Peripherals
UART0
Timers 0,
1, 2
3 Channel
PCA/WDT
C2CK/RST
Debug /
Programming
Hardware
C2D
Priority
Crossbar
Decoder
Port 0
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/C2D
P0.7/XTAL1
P1.0/XTAL2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
VREGIN
VDD
GND
Voltage Regulator
(LDO)
SPI
SFR
Bus
Crossbar Control
Port 1
Drivers
Analog Peripherals
Voltage
Reference
VDD
VREF
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
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System Clock Setup
XTAL1
XTAL2
External Oscillator
Internal Oscillator
(±0.5%)
VREF
12-bit
200ksps
ADC
A
M
U
X
Comparator
Automotive
Copyright © 2008 by Silicon Laboratories
11.20.2008