C8051F80x-83x
CIP-51 8051
Controller Core
Power On
Reset
Reset
Flash Memory
‘F826, ‘F829: 8 kB
‘F832, ‘F835: 4 kB
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1
Timer 2 /
RTC
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
Port 1
Drivers
Port 0
Drivers
RST/C2CK
Debug /
Programming
Hardware
P2.0/C2D
256 Byte RAM
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
Peripheral
Power
SFR
Bus
Core Power
SPI
Crossbar Control
Port 2
Drivers
P2.0/C2D
VDD
Regulator
GND
SYSCLK
Analog Peripherals
+
-
Precision
Internal
Oscillator
XTAL1
XTAL2
External
Clock
Circuit
Comparator
VDD
A
M
U
X
VREG Output
VREF
A
M
U
X
(‘F826, ‘F832 Only)
VREG Output
VDD
12 Channels
Temp Sensor
System Clock
Configuration
10-bit
500 ksps
ADC
Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram
24
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
