C8051F80x-83x
8. 10-Bit ADC (ADC0)
ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 is a
500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain
stage programmable to 1x or 0.5x, and a programmable window detector. The ADC is fully configurable
under software control via Special Function Registers. The ADC may be configured to measure various dif-
ferent signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer” on
(ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
ADC0CN
AD0EN
AD0TM
AD0INT
AD0BUSY
AD0WINT
VDD
Start
Conversion
AD0CM2
AD0CM1
AD0CM0
000
001
010
011
100
From
AMUX0
X1 or
X0.5
AIN
10-Bit
SAR
AMP0GN0
SYSCLK
REF
ADC0H
ADC
ADC0L
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
AD0WINT
Window
Compare
Logic
AD0SC2
AD0SC1
AD0SC0
AD0LJST
AD08BE
AMP0GN0
AD0SC4
AD0SC3
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Figure 8.1. ADC0 Functional Block Diagram
46
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
