C8051F80x-83x
Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values to
Write
Current SMbus State
ACK
Typical Response Options
ACK
1
0
0
1
0
1
0
STO
STA
Vector Expected
197
ARBLOST
ACKRQ
Vector
Status
1110
0
0
0 X
0
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
0
1
0
0
0
0 X
0 X
1 X
0 X
1 X
1 X
0 X
0 X
Master Transmitter
A master data or address byte Set STA to restart transfer.
0 was transmitted; NACK
Abort transfer.
received.
Load next data byte into
SMB0DAT.
1100
0
0
End transfer with STOP.
A master data or address byte End transfer with STOP and start 1
another transfer.
1 was transmitted; ACK
received.
Send repeated START.
1
Switch to Master Receiver Mode 0
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0
0
1
1
Send NACK to indicate last byte, 0
and send STOP.
Send NACK to indicate last byte, 1
and send STOP followed by
START.
1000
1
A master data byte was
0 X
received; ACK requested.
Send ACK followed by repeated
START.
1
Master Receiver
0
0
0
Send NACK to indicate last byte, 1
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0
0
0
Rev. 1.0
Next Status
Values Read
Mode
1100
1110
—
1100
—
—
1110
1000
1000
—
1110
1110
1110
1100
1100
SILABS [ SILICON LABORATORIES ]
