C8051F80x-83x
Table 18.1. Interrupt Summary
Cleared by HW?
Interrupt Source
Interrupt Priority
Vector
Order
Pending Flag
Bit addressable?
Enable
Flag
Priority
Control
Reset
External Interrupt 0
(INT0)
Timer 0 Overflow
External Interrupt 1
(INT1)
Timer 1 Overflow
UART0
Timer 2 Overflow
SPI0
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0033
Top
0
1
2
3
4
5
6
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
N/A N/A Always
Always
Enabled
Highest
Y
Y
EX0 (IE.0) PX0 (IP.0)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
ET2 (IE.5) PT2 (IP.5)
ESPI0
(IE.6)
PSPI0
(IP.6)
SMB0
Port Match
ADC0
Window Compare
ADC0
Conversion Complete
Programmable
Counter Array
Comparator0
RESERVED
RESERVED
CS0 Conversion Com-
plete
CS0 Greater Than
0x003B
0x0043
0x004B
0x0053
0x005B
0x0063
7
8
9
10
11
12
ESMB0
(EIE1.0)
None
N/A N/A EMAT
(EIE1.1)
AD0WINT (ADC0CN.3) Y
N
EWADC0
(EIE1.2)
AD0INT (ADC0CN.5)
Y
N
EADC0
(EIE1.3)
CF (PCA0CN.7)
Y
N
EPCA0
(EIE1.4)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
N
N
ECP0
(EIE1.5)
CP0RIF (CPT0CN.5)
Y
N
PSMB0
(EIP1.0)
PMAT
(EIP1.1)
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
0x007B
0x0083
15
16
CS0INT (CS0CN.5)
CS0CMPF (CS0CN.0)
N
N
N
N
ECSCPT
(EIE2.0)
ECSGRT
(EIE2.1)
PSCCPT
(EIP2.0)
PSCGRT
(EIP2.1)
18.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
104
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
