C8051F80x-83x
SFR Definition 21.1. VDM0CN: V Monitor Control
DD
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT
Type
R/W
R
R
R
R
R
R
R
Reset
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
V
Monitor Enable.
DD
This bit turns the V monitor circuit on/off. The V Monitor cannot generate sys-
DD
DD
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 21.2). Selecting the V monitor as a reset source before it has stabilized
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may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V Monitor and selecting it as a
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reset source. After a power-on reset, the VDD monitor is enabled, and this bit will
read 1. The state of this bit is sticky through any other reset source.
0: V Monitor Disabled.
DD
1: V Monitor Enabled.
DD
6
VDDSTAT
Unused
V
Status.
DD
This bit indicates the current power supply status (V Monitor output).
0: V is at or below the V monitor threshold.
1: V is above the V monitor threshold.
DD
DD
DD
DD
DD
5:0
Read = Varies; Write = Don’t care.
21.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “7. Electrical Characteristics”
on page 39 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exter-
nal reset.
21.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
126
Rev. 1.0
SILICON [ SILICON ]
