C8051F80x-83x
CIP-51 8051
Controller Core
Power On
Reset
Reset
Flash Memory
‘F801/7: 16 kB
‘F813/9: 8 kB
256 Byte RAM
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1
Timer 2 /
RTC
PCA/
WDT
SMBus
Priority
Crossbar
Decoder
Port 1
Drivers
Port 0
Drivers
RST/C2CK
Debug /
Programming
Hardware
P2.0/C2D
256 Byte XRAM
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0/C2D
Peripheral
Power
SFR
Bus
Core Power
SPI
Crossbar Control
Port 2
Drivers
VDD
Regulator
GND
SYSCLK
Analog
Peripherals
+
-
Capacitive
Sense
A
M
U
X
8 Channels
Precision
Internal
Oscillator
XTAL1
XTAL2
External
Clock
Circuit
VREG Output
Comparator
VDD
VREF
A
M
U
X
(‘F801, ‘F813 Only)
VREG Output
VDD
16 Channels
Temp Sensor
System Clock
Configuration
10-bit
500 ksps
ADC
Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram
Rev. 1.0
17
SILABS [ SILICON LABORATORIES ]
