C8051F52x-53x
8/4/2 kB ISP Flash MCU Family
Analog Peripherals
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12-Bit ADC
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Comparator
±1 LSB INL (C8051F52x/C8051F53x); no missing
codes
Programmable throughput up to 200 ksps
Up to 6/16 external inputs
Data dependent windowed interrupt generator
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as wake-up or reset source
Low current
Memory
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8/4/2 kB Flash; In-system byte programmable in
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Digital Peripherals
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16/6 port I/O; push-pull or open-drain, 5 V tolerant
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Hardware SPI™, and UART serial port
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Hardware LIN (both master and slave, compatible
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with V1.3 and V2.0)
Three general purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with three
capture/compare modules, WDT
512 byte sectors
256 bytes internal data RAM
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POR/Brownout Detector
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Voltage Reference—1.5 to 2.2 V (programmable)
On-Chip Debug
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On-chip debug circuitry facilitates full-speed, non-
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Supply Voltage 2.7 to 5.25 V
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Built-in LDO regulator
High Speed 8051 µC Core
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Pipelined instruction architecture; executes 70% of
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instructions in 1 or 2 system clocks
Up to
25 MIPS
throughput with
25 MHz system clock
Expanded interrupt handler
intrusive in-system debug (No emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
Clock Sources
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Internal oscillators: 24.5 MHz
±0.5%
accuracy sup-
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ports UART and LIN-Master operation
External oscillator: Crystal, RC, C, or Clock
(1 or 2 pin modes)
Can switch between clock sources on-the-fly
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Packages:
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10-Pin QFN (3 x 3 mm)
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20-pin QFN (4 x 4 mm)
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20-pin TSSOP
Temperature Range: –40 to +125 °C
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SPI
PCA
Timer 0
Timer 1
Timer 2
Port 0
CROSSBAR
Port 1
LIN
12-bit
200 ksps
ADC
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VOLTAGE
COMPARATOR
TEMP
SENSOR
VREF
VREG
24.5 MHz High Precision (±0.5%) Internal Oscillator
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
WDT
Rev. 0.3 5/07
Copyright © 2007 by Silicon Laboratories
C8051F52x-53x
SILABS [ SILICON LABORATORIES ]
