CP2102
4. Pinout and Package Definitions
Table 5. CP2102 Pin Definitions
Name
V
DD
Pin #
6
Type
Power In
Description
3.0–3.6 V Power Supply Voltage Input.
Power Out 3.3 V Voltage Regulator Output. See
GND
RST
3
9
D I/O
Ground
Device Reset. Open-drain output of internal POR or V
DD
monitor. An
external source can initiate a system reset by driving this pin low for
at least 15 µs.
5 V Regulator Input. This pin is the input to the on-chip voltage regu-
lator.
VBUS Sense Input. This pin should be connected to the VBUS sig-
nal of a USB network. A 5 V signal on this pin indicates a USB net-
work connection.
USB D+
USB D–
Asynchronous data output (UART Transmit)
Asynchronous data input (UART Receive)
Clear To Send control input (active low)
Ready to Send control output (active low)
Data Set Ready control input (active low)
Data Terminal Ready control output (active low)
Data Carrier Detect control input (active low)
Ring Indicator control input (active low)
This pin is driven high when the CP2102 enters the USB suspend
state.
This pin is driven low when the CP2102 enters the USB suspend
state.
These pins should be left unconnected or tied to V
DD
.
REGIN
VBUS
7
8
Power In
D In
D+
D–
TXD
RXD
CTS
RTS
DSR
DTR
DCD
RI
SUSPEND
SUSPEND
NC
4
5
26
25
23*
24*
27*
28*
1*
2*
12*
11*
10, 13–22
D I/O
D I/O
D Out
D In
D In
D Out
D in
D Out
D In
D In
D Out
D Out
*Note:
Pins can be left unconnected when not used.
6
Rev. 1.2
SILABS [ SILICON LABORATORIES ]
