Si1000/1/2/3/4/5
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si1000/1/2/3/4/5 device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
DATA MEMORY
(RAM)
INTERNAL DATA ADDRESS SPACE
Si1000/2
Upper 128 RAM
Special Function
Registers
0x03FF
0x0000
0xFFFF
Scrachpad Memory
(DATA only)
(Indirect Addressing Only) (Direct Addressing Only)
0
F
RESERVED
(Direct and Indirect
Addressing)
0xFC00
0xFBFF
Lower 128 RAM
(Direct and Indirect
Addressing)
64KB FLASH
Bit Addressable
(In-System
Programmable in 1024
Byte Sectors)
General Purpose
Registers
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Si1001/3
0x03FF
0x0000
Scrachpad Memory
(DATA only)
Reserved
0x7FFF
0x1000
0x0FFF
32KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0x0000
0x0000
Figure 9.1. Si1000/1/2/3/4/5 Memory Map
118
Rev. 1.0
SILICON [ SILICON ]
