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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
0.68 uH  
1 uF  
DC-DC Converter  
Enabled  
4.7 uF  
0.9 to 1.8 V   
Supply Voltage  
GND_MCU/  
VBAT GND/VBAT- DCEN  
DC-  
VDD_MCU/  
DC+  
(one-cell mode)  
VBAT GND/VBAT- DCEN  
GND_MCU/  
DC-  
DC-DC Converter  
Disabled  
VDD_MCU/  
DC+  
1.8 to 3.6 V   
Supply Voltage  
(two-cell mode)  
Figure 16.2. DC-DC Converter Configuration Options  
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines  
apply:  
In most cases, the GND/VBAT– pin should not be externally connected to GND.  
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.  
The 4.7 µF capacitor should be placed as close as possible to the inductor.  
The current loop including GND/VBAT-, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin  
should be made as short as possible to minimize capacitance.  
The PCB traces connecting VDD_MCU/DC+ to the output capacitor and the output capacitor to  
GND_MCU/DC– should be as short and as thick as possible in order to minimize parasitic inductance.  
16.5. Minimizing Power Supply Noise  
To minimize noise on the power supply lines, the GND/VBAT- and GND_MCU/DC- pins should be kept  
separate, as shown in Figure 16.2; GND_MCU/DC- should be connected to the pc board ground plane.  
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet  
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g., connecting an  
external chip between VDD_MCU/DC+ and GND/VBAT-, or between VBAT and GND_MCU/DC-) can  
result in high supply noise across that circuit element.  
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external  
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section  
5.12. This option prevents any voltage differences between the internal chip ground and the external  
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the  
168  
Rev. 1.0