Si1000/1/2/3/4/5
18.1. Power-On (VBAT Supply Monitor) Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
settles above
BAT
V
V
. An additional delay occurs before the device is released from reset; the delay decreases as the
POR
ramp time increases (V
ramp time is defined as how fast V
ramps from 0 V to V
).
=
BAT
BAT
BAT
POR
Figure 18.3 plots the power-on and V
monitor reset timing. For valid ramp times (less than 3 ms), the
DD
power-on reset delay (T
3.6 V).
) is typically 3 ms (V
= 0.9 V), 7 ms (V
= 1.8 V), or 15 ms (V
BAT
PORDelay
BAT
BAT
Note: The maximum VDD ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before VBAT reaches the VPOR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
Note: Si1000/1/2/3 have the VBAT signal internally connected to VDD_MCU.
VBAT
VPOR
~0.8
0.6
~0.5
See specification
table for min/max
voltages.
t
RST
Logic HIGH
Logic LOW
TPORDelay
TPORDelay
Power-On
Reset
Power-On
Reset
Figure 18.2. Power-Fail Reset Timing Diagram
176
Rev. 1.0
SILICON [ SILICON ]
