Si1000/1/2/3/4/5
SFR Definition 24.2. SMB0CN: SMBus Control
Bit
Name
Type
Reset
7
MASTER
R
0
6
TXMODE
R
0
5
STA
R/W
0
4
STO
R/W
0
3
ACKRQ
R
0
2
ARBLOST
R
0
1
ACK
R/W
0
0
SI
R/W
0
SFR Page = 0x0; SFR Address = 0xC0; Bit-Addressable
Bit
Name
Description
7
MASTER
SMBus Master/Slave
Indicator.
This read-only bit
indicates when the SMBus is
operating as a master.
TXMODE
SMBus Transmit Mode
Indicator.
This read-only bit
indicates when the SMBus is
operating as a transmitter.
STA
Read
N/A
Write
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
6
N/A
5
SMBus Start Flag.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted after the next ACK
cycle.
Cleared by Hardware.
N/A
N/A
0: Send NACK
1: Send ACK
0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
4
STO
SMBus Stop Flag.
3
2
1
0
ACKRQ
SMBus Acknowledge
Request.
0: No Ack requested
1: ACK requested
0: No arbitration error.
1: Arbitration Lost
0: NACK received.
1: ACK received.
ARBLOST
SMBus Arbitration Lost
Indicator.
ACK
SI
SMBus Acknowledge.
SMBus Interrupt Flag.
0: No interrupt pending
This bit is set by hardware
1: Interrupt Pending
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
Rev. 1.0
295
SILABS [ SILICON LABORATORIES ]
