Si1000/1/2/3/4/5
28.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 28.1. PCA0CN: PCA Control
Bit
Name
Type
Reset
7
CF
R/W
0
6
CR
R/W
0
5
CCF5
R/W
0
4
CCF4
R/W
0
3
CCF3
R/W
0
2
CCF2
R/W
0
1
CCF1
R/W
0
0
CCF0
R/W
0
SFR Page = 0x0; SFR Address = 0xD8; Bit-Addressable
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared
by hardware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:0
CCF[5:0]
PCA Module n Capture/Compare Flag.
These bits are set by hardware when a match or capture occurs in the associated PCA
Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by
hardware and must be cleared by software.
Rev. 1.0
365
SILABS [ SILICON LABORATORIES ]
