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Si1000/1/2/3/4/5

15. Cyclic Redundancy Check Unit (CRC0)

Si1000/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a

16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0

posts the 16-bit or 32-bit result to an internal register. The internal result register may be accessed indi-

rectly using the CRC0PNT bits and CRC0DAT register, as shown in Figure 15.1. CRC0 also has a bit

reverse register for quick data manipulation.

CRC0IN

8

8

Automatic CRC

Controller

Flash

Memory

CRC0CN

CRC0SEL

CRC0INIT

CRC0VAL

CRC0PNT1

CRC0PNT0

CRC0FLIP

Write

CRC0AUTO

CRC Engine

32

RESULT

8

8

8

4 to 1 MUX

8

CRC0DAT

8

CRC0CNT

CRC0FLIP

Read

Figure 15.1. CRC0 Block Diagram

15.1. CRC Algorithm

The Si1000/1/2/3/4/5 CRC unit generates a CRC result equivalent to the following algorithm:

1. XOR the input with the most-significant bits of the current CRC result. If this is the first iteration of the

CRC unit, the current CRC result will be the set initial value



(0x00000000 or 0xFFFFFFFF).

2a. If the MSB of the CRC result is set, shift the CRC result and XOR the result with the selected

polynomial.

2b. If the MSB of the CRC result is not set, shift the CRC result.

Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-

ple.

The 16-bit Si1000/1/2/3/4/5 CRC algorithm can be described by the following code:

unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)

{

unsigned char i;

// loop counter

#define POLY 0x1021

158

Rev. 1.0