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SI1010-A-GM 参数 Datasheet PDF下载

SI1010-A-GM图片预览
型号: SI1010-A-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 16/8 KB ,第12/ 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 16/8 kB, 12/10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 384 页 / 2424 K
品牌: SILABS [ SILICON LABORATORIES ]
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Si1010/1/2/3/4/5
11. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si1010/1/2/3/4/5's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the
Si1010/1/2/3/4/5. This allows the addition of new functionality while retaining compatibility with the MCS-
51™ instruction set. Table 11.1 and Table 11.2 list the SFRs implemented in the Si1010/1/2/3/4/5 device
family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
SPI0CN
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
B
P0MDIN
P1MDIN
SMB0ADR
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
ACC
XBR0
XBR1
XBR2
IT01CF
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
PSW
REF0CN PCA0CPL5 PCA0CPH5 P0SKIP
TMR2CN REG0CN TMR2RLL TMR2RLH
TMR2L
SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH
IP
IREF0CN ADC0AC ADC0MX
ADC0CF
SPI1CN OSCXCN OSCICN
OSCICL
IE
CLKSEL
EMI0CN
RTC0ADR
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT
SCON0
SBUF0
CPT1CN
CPT0CN
CPT1MD
P1
TMR3CN TMR3RLL TMR3RLH
TMR3L
TCON
TMOD
TL0
TL1
TH0
P0
SP
DPL
DPH
SPI1CFG
0(8)
1(9)
2(A)
3(B)
4(C)
(bit addressable)
PCA0CPL4
SMB0ADM
PCA0CPL3
FLWR
PCA0CPM3
P1SKIP
TMR2H
ADC0LTL
ADC0L
PMU0CF
RTC0DAT
P1MDOUT
CPT0MD
TMR3H
TH1
SPI1CKR
5(D)
PCA0CPH4 VDM0CN
EIP1
EIP2
PCA0CPH3 RSTSRC
EIE1
EIE2
PCA0CPM4 PCA0PWM
P0MAT
PCA0CPM5
P1MAT
ADC0LTH
P0MASK
ADC0H
P1MASK
FLSCL
FLKEY
RTC0KEY
P2MDOUT SFRPAGE
CPT1MX
CPT0MX
DC0CF
DC0CN
CKCON
PSCTL
SPI1DAT
PCON
6(E)
7(F)
128
Rev. 1.0