Si1010/1/2/3/4/5
Table 3.1. Pin Definitions for the Si1010/1/2/3/4/5 (Continued)
Name
Pin Number
Type
Description
Si1010/1
Si1012/3
Si1014/5
RST/
39
42
D I/O Device Reset. Open-drain output of internal POR or V
DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. A 1–5 k pullup to
VDD_MCU is recommended. See Reset Sources section
for a complete description.
C2CK
P2.7/
D I/O
Clock signal for the C2 Debug Interface.
40
1
D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar
cannot route signals to this pin and it cannot be configured
as an analog input. See Port I/O section for a complete
description.
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
XTAL3
1
3
2
A In
SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
XTAL4
P0.0
42
36
A Out SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
36
D I/O or Port 0.0. See Port I/O section for a complete description.
A In
A In
V
External V
Input.
REF
REF
A Out
Internal V
Output. External V
decoupling capacitors
REF
REF
are recommended. See Voltage Reference section.
P0.1
35
34
35
34
D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
G
AGND
P0.2
Optional Analog Ground. See VREF chapter.
D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
A In
XTAL1
P0.3
External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator section.
33
33
D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
A Out
D In
XTAL2
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
A In
See Oscillator section for complete details.
Rev. 1.0
33
SILICON [ SILICON ]
