Si102x/3x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power at 3.6V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
110 µA/MHz IBAT; DC-DC enabled
110 nA sleep current with data retention; POR monitor enabled
400 nA sleep current with smaRTClock (internal LFO)
700 nA sleep current with smaRTClock (external XTAL)
2 µs wake-up from any sleep mode
Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode
External pin or internal VREF (no external capacitor required)
On-chip PGA allows measuring voltages up to twice the reference
voltage
Autonomous burst mode with 16-bit automatic averaging accumu-
lator
Integrated temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Up to ±500 µA; source and sink capability
Enhanced resolution via PWM interpolation
Supports up to 128 segments (32x4)
Integrated charge pump for contrast control
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Sleep-mode pulse accumulator with programmable switch
de-bounce and pull-up control interfaces directly to metering sen-
sor
Dedicated Packet Processing Engine (DPPE) includes hardware
AES, DMA, CRC, and encoding blocks for acceleration of wireless
protocols
Manchester and 3 out of 6 encoder hardware for power efficient
implementation of the wireless M-bus specification
®
Frequency range = 240–960 MHz
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm or +13 dBm
12-Bit; 16 Ch. Analog-to-Digital Converter
RF power consumption
18.5 mA receive
18 mA @ +1 dBm transmit
30 mA @ +13 dBm transmit
85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64-byte FIFOs
Frequency hopping capability
On-chip crystal tuning
Pipelined instruction architecture; executes 70% of instructions in 1
or 2 system clocks
Up to 128 kB Flash; In-system programmable; Full read/write/erase
functionality over the entire supply range
Up to 8 kB internal data RAM
53 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
Hardware SMBus™ (I2C™ compatible), 2 x SPI™, and UART
serial ports available concurrently
Four general-purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with six capture/compare
modules and watchdog timer
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
ports UART operation; spread-spectrum mode for reduced EMI
Low power internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
On-chip debug circuitry facilitates full-speed, non-intrusive, in-sys-
tem debug (no emulator required)
Provides 4 breakpoints, single stepping
–85 pin LGA (6 x 8 mm)
High-Speed 8051 µC Core
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Memory
Two Low Current Comparators
Internal 6-Bit Current Reference
Integrated LCD Controller (Si102x Only)
Metering-Specific Peripherals
Digital Peripherals
Clock Sources
On-Chip Debug
EZRadioPRO Transceiver
Packages
Power On
Reset/PMU
Wake
Reset
CIP-51 8051
Controller Core
128/64/32/16 kByte
ISP Flash Program
Memory
256 Byte SRAM
8192/4096 Byte XRAM
DMA
Analog
Power
Port I/O Configuration
Digital Peripherals
UART
Timers
0/1/2/3
PCA/
WDT
SMBus
SPI 0
Crossbar Control
LCD (4x32)
Port 0-1
Drivers
Port 2
Drivers
16
P0.0...P1.7
4
P2.4...P2.7
32
C2CK/RST
Debug /
Programming
Hardware
C2D
Priority
Crossbar
Decoder
Port 3-6
Drivers
Port 7
Driver
P3.0...P6.7
P7.0/C2D
VBAT
VDC
VBAT
VDD
CRC
Engine
AES
Engine
Encoder
RF XCVR
(240-960 MHz,
+20/+13 dBm)
VCO
VREG
Digital
Power
PA
TX
AGC
VBATDC
IND
GNDDC
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
LCD Charge
Pump
XTAL1
XTAL2
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
SYSCLK
SFR
Bus
EMIF
Pulse Counter
EZRadioPro SPI 1
LNA
Mixer
PGA
RXp
RXn
CAP
Analog Peripherals
Internal
VREF
External
VREF
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
CP1, CP1A
+
-
ADC
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
GND
XTAL3
XTAL4
12-bit
75ksps
ADC
3
SDN
nIRQ
GPIOx
XOUT
XIN
System Clock
Configuration
30 MHz
+
-
Comparators
Rev. 0.3 11/11
Copyright © 2011 by Silicon Laboratories
Si102x/3x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
