S i 2 1 0 7 / 0 8 / 0 9 /1 0
S
ATELLITE
R
ECEIVER
Features
Single-chip tuner, demodulator,
and LNB controller
DVB-S- and DSS-compliant
QPSK/BPSK demodulation
Integrated step-up dc-dc
converter for LNB power supply
(Si2108/10 only)
Input signal level:
–81 to –18 dBm
Symbol rate range:
1 to 45 MBaud
Automatic acquisition and fade
recovery
Automatic gain control
On-chip blind scan accelerator
(Si2109/10 only)
DiSEqC™ 2.2 support
Power, C/N, and BER estimators
I2C bus interface
3.3/1.8 V supply, 3.3 V I/O
Lead-free/RoHS-compliant
package
VDD_LNA
REXT
FOR
DVB-S/DSS
Pin Assignments
Si2107/08/09/10
GND
GND
VDD_SYNTH
35
VDD_LO
RFIN2
RFIN1
RFIP2
RFIP1
GND
Applications
Set-top boxes
Digital video recorders
Digital televisions
Satellite PC-TV
SMATV trans-modulators
(Satellite Master Antenna TV)
44 43 42 41 40 39 38 37 36
1
2
3
4
5
6
7
8
9
10
11
12
13
XTAL1
XTAL2
VDD_XTAL
XTOUT
VDD_PLL33
INT/RLK/GPO
TS_ERR
TS_VAL
TS_SYNC
SDA
SCL
TS_DATA[7]
TS_DATA[6]
GND
34
33
32
ADDR
VDD_MIX
VDD_BB
VDD_ADC
VSEN/TDET
LNB1/TGEN
ISEN
Top
View
GND
14 15 16 17 18 19 20 21 22
VDD_DIG33
TS_DATA[0]
TS_DATA[1]
TS_DATA[2]
TS_DATA[3]
VDD_DIG33
TS_CLK
TS_DATA[4]
TS_DATA[5]
31
30
29
28
27
26
25
24
23
Description
The Si2107/08/09/10 are a family of pin-compatible, complete front-end solutions
for DSS and DVB-S digital satellite reception. The IC family incorporates a tuner,
demodulator, and LNB controller into a single device resulting in significantly
reduced board space and external component count. The device supports symbol
rates of 1 to 45 MBaud over a 950 to 2150 MHz range. A full suite of features
including automatic acquisition, fade recovery, blind scanning, performance
monitoring, and DiSEqC Level 2.2 compliant signaling are supported. The Si2108/
10 further add short circuit protection, overcurrent protection, and a step-up dc-dc
controller to implement a low-cost LNB supply solution. Si2110/09 versions
include a hardware channel scan accelerator for fast “blindscan”. An I2C bus
interface is used to configure and monitor all internal parameters.
LNB2/DRC
RESET
PWM/DCS
VDD_DIG18
Functional Block Diagram
AGC
Acquisition Control
A/D Converter
De-interleaver
Descrambler
RFIP
Tuner
Demodulator
Viterbi
Decoder
RS
Decoder
TS_CLK
TS_DATA[7:0]
TS_VAL
TS_SYNC
TS_ERR
VSEN/TDET
LNB2/DRL
ISEN/NC
LNB1/TGEN
PWM/DCS
LNB Control
RF Sythesizer
I2C Interface
MPEG-TS
INT/RLK/GPO
XOUT
SCL
SDA
Preliminary Rev. 0.7 3/06
Copyright © 2006 by Silicon Laboratories
Si2107/08/09/10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SILABS [ SILICON LABORATORIES ]
