Si2107/08/09/10
Table 7. I
2
C Bus Characteristics
Parameter
SCL Clock Frequency
Bus Free Time between START and
STOP Condition
Hold Time (repeated) START Condition.
(After this period, the first clock pulse is
generated.)
LOW Period of SCL Clock
HIGH Period of SCL Clock
Data Setup Time
Data Hold Time
SCL and SDA Rise and Fall Time
Setup Time for a Repeated START Con-
dition
Setup Time for STOP Condition
Capacitive Load for each Bus Line
Symbol
f
SCL
t
BUF
t
HD, STA
Test Condition
Min
0
1.3
0.6
Typ
—
—
—
Max
400
—
—
Unit
kHz
µs
µs
t
LOW
t
HIGH
t
SU, DAT
t
HD, DAT
t
r,
t
f
t
SU, STA
t
SU,STO
C
B
1.3
0.6
100
0
—
0.6
0.6
—
—
—
—
—
—
—
—
—
—
—
—
0.9
300
—
—
400
µs
µs
ns
µs
ns
µs
µs
pF
SDA
t
f
t
LOW
t
r
t
SU;DAT
t
f
t
HD;STA
t
SP
t
r
t
BUF
SCL
S
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
S
r
t
SU;STO
P
S
Figure 1. I
2
C Timing Diagram
8
Preliminary Rev. 0.81
SILABS [ SILICON LABORATORIES ]
