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SI3056DC-EVB 参数 Datasheet PDF下载

SI3056DC-EVB图片预览
型号: SI3056DC-EVB
PDF下载: 下载PDF文件 查看货源
内容描述: 全球串行接口直接访问安排 [GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT]
分类和应用:
文件页数/大小: 94 页 / 1395 K
品牌: SILABS [ SILICON LABORATORIES ]
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Si3056
S i 3 0 1 8 / 1 9 / 10
G
LOBAL
S
ERIAL
I
NTERFACE
D
IRECT
A
CCESS
A
RRANGEMENT
Features
Complete DAA includes the following:
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
80 dB dynamic range TX/RX paths
Integrated codec and 2- to 4-wire
hybrid
Integrated ring detector
Type I and II caller ID support
Line voltage monitor
Loop current monitor
Polarity reversal detection
Programmable digital gain
Clock generation
Pulse dialing support
Overload detection
3.3 V power supply
Direct interface to DSPs
Serial interface control for up to eight
devices
>5000 V isolation
Proprietary isolation technology
Parallel handset detection
+3.2 dBm TX/RX level mode
Programmable digital hybrid for near-
end echo reduction
Low-profile SOIC packages
Lead-free/RoHS-compliant packages
available
Ordering Information
See page 88.
Pin Assignments
Si3056
MCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OFHK
RGDT/FSD/M1
M0
V
A
GND
AOUT/INT
C1A
C2A
Applications
V.92 modems
Voice mail systems
Multi-function printers
Set-top boxes
Fax machines
Internet appliances
Personal digital
assistants
FSYNC
SCLK
V
D
SDO
SDI
FC/RGDT
RESET
Description
The Si3056 is an integrated direct access arrangement (DAA) with a
programmable line interface to meet global telephone line requirements. Available
in two 16-pin small outline packages, it eliminates the need for an analog front end
(AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The
Si3056 dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The Si3056
interfaces directly to standard modem DSPs.
Si3018/19/10
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCT2
IGND
DCT3
QB
QE2
SC
VREG2
RNG2
Functional Block Diagram
Si3056
MCLK
SCLK
FSYNC
SDI
SDO
FC/RGDT
Si3018/19/10
RX
Digital
Interface
Hybrid and
dc
Termination
Isolation
Interface
Isolation
Interface
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
RGDT/FSD/M1
OFHK
M0
RESET
AOUT/INT
Control
Interface
Ring Detect
Off-Hook
Rev. 1.05 6/05
Copyright © 2005 by Silicon Laboratories
Si3056