Si3215
5. Pin Descriptions: Si3215
QFN
TSSOP
38
37
1
2
CS
INT
SCLK
SDI
PCLK
DRX
DTX
FSYNC
RESET
SDCH
SDCL
VDDA1
IREF
CAPP
QGND
CAPM
36 SDO
3
4
5
6
7
8
9
10
11
12
13
14
38 37 36 35 34 33 32
1
DTX
FSYNC
RESET
SDCH
SDCL
VDDA1
31 SDITHRU
35
34
33
32
31
30
SDITHRU
30
2
3
4
DCDRV
DCDRV
DCFF
TEST
GNDD
VDDD
29
DCFF
28
27
26
25
24
23
22
21
20
TEST
GNDD
VDDD
ITIPN
ITIPP
5
6
7
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
29 ITIPN
8
28
27
ITIPP
VDDA2
9
VDDA2
10
11
12
26 IRINGP
IRINGP
IRINGN
IGMP
25
24
23
22
21
20
IRINGN
IGMP
GNDA
IGMN
SRINGAC
STIPAC
STIPDC 15
SRINGDC 16
STIPE
SVBAT 18
SRINGE
13 14 15 16 17 18 19
17
19
Pin #
QFN TSSOP
Pin #
Name
Description
35
1
CS
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance.
When active, the serial port is operational.
36
37
38
1
2
3
4
5
6
INT
PCLK
DRX
DTX
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
Transmit PCM Data.
Output data to PCM bus.
2
FSYNC Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse for-
mat.
3
4
7
8
RESET Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
SDCH
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
Rev. 0.92
107
SILICON [ SILICON ]
