Si3452/3
Description
When connected directly to the host system or configured in Auto mode, each Si3452/3 high-voltage port controller
provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage
interfaces of four complete PSE ports. The Si3452/3 fully integrates robust, low-R
ON
(0.3
typical) power
MOSFET switches, low-power dissipation current sensing circuitry, and transient voltage surge suppression
devices.
The on-chip current sense circuitry and power MOSFETs provide programmable scaling of current limits to match
either PoE (350 mA, 15.4 W), PoE+ (600 mA, 30 W), and extended (800 mA, 40 W) power requirements on a per-
port basis. Designed for use in Endpoint PSE (e.g., Ethernet switches) or Midspan PSE (e.g., inline power
injectors) applications, each Si3452/3 also performs the IEEE-required powered device (PD) detection,
classification, and disconnect functionality.
The flexible architecture enables powered device disconnect detection using either dc disconnect (Si3453) or
Silicon Laboratories' proprietary dV/dt disconnect (Si3452) sensing algorithm. dV/dt disconnect is an alternative to
dc disconnect that requires no additional BOM components, does not dissipate extra device power, and fully
interoperates with all powered devices. Also provided are multi-point detection algorithms and per-port current and
voltage monitoring.
Intelligent protection circuitry includes power supply under-voltage lockout (UVLO), port output current limiting and
short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge-suppressors
capable of protecting the Si3452/3 from a variety of harsh surge events seen on the RJ-45 interface.
To maximize system design flexibility and minimize cost, each Si3452/3 connects directly to a system host
controller through an I
2
C serial interface, eliminating the need for an external MCU. The Si3452/3 can be set to one
of 12 unique addresses, allowing control of up to 48 ports on a single I
2
C bus.
Functional Block Diagram
GND34
GND12
RST
AD2
AD3
AD1
AD0
RST
AD3
AD2
AD1
AD0
MCU Core
& PSE FSM
LV SPI
HV SPI
&
Port
Control
Channel
Mode
&
Limit
Control
PER PORT ANALOG
Detection
&
Classification
DC or
dV/dt
Disconnect
Gate Control,
Current Limit
& Foldback
Thermal
Prot.
DET4
DET3
DET2
DET1
256 Byte SRAM
8 kByte EPROM
PLL
POR
PGA
Temp
Sensor
MEAS.
MUX
WDT
10b
ADC
AMUX
VOUT4
VOUT3
VOUT2
I2C
Voltage
Regulator
& Monitor
VREF & Central Bias
Current
Sense
VOUT1
VEE1
VEE2
VEE3
AGND
RBIAS
DGND
VREF
2
AGND
AOUT
VDD
Rev. 1.0
VEE4
VDD
INT
SDA
VEE
SCL
AIN
SILABS [ SILICON LABORATORIES ]
