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SI5010 参数 Datasheet PDF下载

SI5010图片预览
型号: SI5010
PDF下载: 下载PDF文件 查看货源
内容描述: OC - 12/3 , STM - 4/1 SONET / SDH时钟和数据恢复IC [OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC]
分类和应用: 时钟
文件页数/大小: 20 页 / 277 K
品牌: SILABS [ SILICON LABORATORIES ]
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Si5010
OC-12/3, STM-4/1 SONET/SDH C
LOCK AND
D
ATA
R
ECOVERY
IC
Features
Complete CDR solution includes the following:
Supports OC-12/3, STM-4/1
Low power, 293 mW (TYP OC-12)
Small footprint: 4x4 mm
DSPLL™ eliminates external loop
filter components
3.3 V tolerant control inputs
Exceeds All SONET/SDH jitter
specifications
Jitter generation
1.6 mUI
rms
(typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V supply
Ordering Information:
See page 16.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Pin Assignments
Si5010
CLKOUT+
CLKOUT–
15
RATESEL
GND
Description
The Si5010 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-12/3 or STM-4/1 data
rates. DSPLL
®
technology eliminates sensitive noise entry points thus
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter,
low-power, and small size for high-speed CDRs. It operates from a single
2.5 V supply over the industrial temperature range (–40 to 85 °C).
REXT
VDD
GND
REFCLK+
REFCLK–
1
2
3
4
5
NC
20 19 18 17 16
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
GND
Pad
Connection
6
LOL
7
VDD
8
GND
9
DIN+
10
DIN–
14
13
12
11
Top View
Functional Block Diagram
LOL
DIN+
DIN–
2
BUF
DSPLL
TM
Phase-Locked
Loop
Retim er
BUF
2
DOUT+
DOUT–
PW RDN/CAL
Bias
2
BUF
2
CLKOUT+
CLKOUT–
REXT
RATESEL
REFCLK+
REFCLK–
Rev. 1.3 12/04
Copyright © 2004 by Silicon Laboratories
Si5010