欢迎访问ic37.com |
会员登录 免费注册
发布采购

SI5110 参数 Datasheet PDF下载

SI5110图片预览
型号: SI5110
PDF下载: 下载PDF文件 查看货源
内容描述: SiPHY⑩ OC- 48 / STM - 16 SONET / SDH收发器 [SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER]
分类和应用:
文件页数/大小: 26 页 / 399 K
品牌: SILABS [ SILICON LABORATORIES ]
 浏览型号SI5110的Datasheet PDF文件第2页浏览型号SI5110的Datasheet PDF文件第3页浏览型号SI5110的Datasheet PDF文件第4页浏览型号SI5110的Datasheet PDF文件第5页浏览型号SI5110的Datasheet PDF文件第6页浏览型号SI5110的Datasheet PDF文件第7页浏览型号SI5110的Datasheet PDF文件第8页浏览型号SI5110的Datasheet PDF文件第9页  
S i 5 11 0
P
R E L I M I N A R Y
D
A TA
S
H E E T
S iPH Y
OC- 48/S TM- 16 S O NE T/S DH T
R A N S C E I V E R
Features
Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
Data Rates Supported:
SONET Compliant Loop Timed
OC-48/STM-16 and 2.7 Gbps FEC
Operation
Low Power Operation 1.0 W (typ)
Programmable Slicing Level and
Sample Phase Adjustment
DSPLL™ Based Clock Multiplier Unit
w/ Selectable Loop Filter Bandwidths
LVDS Parallel Interface
Integrated Limiting Amplifier
Single Supply 1.8 V Operation
Diagnostic and Line Loopbacks
11 x 11 mm BGA Package
Si5110
Bottom View
Applications
Sonet/SDH Transmission
Systems
Optical Transceiver Modules
Sonet/SDH Test Equipment
Ordering Information:
See page 23.
Description
The Si5110 is a complete low-power transceiver for high-speed serial
communication systems operating between 2.5 Gbps and 2.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:4 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 4:1 serializer. The CMU uses Silicon Laboratories’
DSPLL
technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing, and sample phase
adjustment are supported.
The Si5110 operates from a single 1.8 V supply over the industrial temperature
range (–40°C to 85°C).
Functional Block Diagram
P H AS E AD J
S L IC E L V L
LO S
LOSLVL
1:4
DEMUX
R X D IN
RE FS EL
Loopback Control
REFCLK
LPTM
R E F R AT E
TX L O L
BW SEL
TX C L K D S B L
TXCLKOUT
TXS Q LCH
TX D O U T
RES E T
2
4:1
MUX
FIFO
2
RE S ET
C o n tro l
LLBK
DLBK
2
T X C L K 4 IN
2
L im itin g
AM P
RXLO L
RX SQ LCH
RXM S BSE L
8
L TR
CDR
R X D O U T[ 3 : 0
2
÷
2
RXCLK1
RXCLK2
R X C L K 2 D IV
RXCLK2DSB
D S P L L
tm
TX CM U
÷
2
2
8
T X C L K 4O UT
T X C L K 4 IN
T X D IN [ 3 : 0 ]
F IF O R S T
F IF O E R R
TX M S B S E L
Preliminary Rev. 0.41 8/01
Copyright © 2001 by Silicon Laboratories
Si5110-DS041
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.